User manual INTEL Q45 EXPRESS CHIPSET EMBEDDED

[. . . ] Intel® CoreTM 2 Duo Processor and Intel® Q45 Express Chipset Development Kit User’s Manual October 2008 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. [. . . ] Rear Speaker Out (Black) This audio jack is used to connect to rear speakers in a 5. 1 and 7. 1-channel audio configuration. 16 2. 6. 2 RJ-45 LAN Connector with Integrated LEDs Two LEDs are built into the RJ-45 LAN connector (as shown in Figure 2-10). Table 2-1 describes the LED states when the board is powered up and the Gigabit LAN subsystem is operating. Figure 2-10: LAN Connector LED locations LED Left Color Green N/A Green Yellow Right LED State Off On Blinking Off On On Condition LAN link is not established. 10 Mbits/sec data rate is selected 100 Mbits/sec data rate is selected 1000 Mbits/sec data rate is selected Table 2-1: LAN Connector LED status 2. 6. 3 USB Port The USB port supports the USB 1. 1/2. 0 specification. 2. 6. 4 HDMI Port This connector provides digital audio input and output from external audio system that supports digital audio data. Please ensure that the audio system provides a HDMI connector. 17 2. 7 Debug Features 2. 7. 1. Extended Debug Probe (XDP) The reference board provides a JTAG-compliant test access port (TAP) for attachment of an XDP connector. The XDP connector and associated circuitry enable the use of the ITP for the particular processor to interrupt the boot sequence and view processor status. The XDP connector is located on the backside of the board at location J2BC. Refer to diagram below for the ITP-XDP SSA connector. Figure 2-11 ITP-XDP Connector location (J2BC) ITP-XDP Connector ITP-XDP SSA Connector is needed in order to connect to ITP-XDP2/3 tools 18 2. 7. 2 Power LEDs Power LEDs on the board indicate when standby power is being applied to the standby planes. When lit they indicate that no DIMM modules should be inserted or removed. To install or replace DIMM modules insure that AC power to the power supply is removed by unplugging the AC power cord from the power supply or placing the switch on the power supply to the open position. Caution: Removing DIMM modules when the standby power LEDs is lit could result in damage to the memory devices on those modules. 2. 7. 3 Port 80 POST Code LEDs Two LEDs display the POST codes output from Port 80 to indicate the progress of the boot sequence or display the POST code of the last operation successfully completed during the boot sequence. Please refer to Chapter 3. 4 for more information on Port 80 code reference. 2. 7. 4 Voltage Reference See Table 2-2 for details of the expected voltage levels for each voltage rail on the CRB. Table 2-2 Voltage Reference detail Voltage Rail VCC VCC3 +12V -12V V_5P0_STBY\G V_3P3_STBY\G V_1P5_ICH VCC_DMI V_FSB_VTT VCCP Expected Voltage 5. 0 3. 3 12 -12 5. 0 3. 3 1. 5 1. 1 1. 1 1. 15-1. 50 Voltage Rail V_1P1_CORE V_1P1_CL_MCH V_1P1_PCIEXPRESS V_SM V_SM_VTT V_1P1_CL V_3P3_PCIVAUX VDD_CLK VCC_CPU_IO Expected Voltage 1. 1 1. 1 1. 1 1. 5 0. 75 1. 1 3. 3 3. 3 1. 1 19 2. 8 Development Kit’s Major Connector & Jumper Figure 2-12 shows major jumpers and headers use on the development kits. J4LB/J10LB J6LB J14LB J7LB J15LB J115LB J16LB Figure 2-12 Major jumpers and headers location on the development kits. 2. 8. 1 Jumper Functions Table 2-3 provides a list of the setting definitions Eaglelake CRB. Table 2-3 Eaglelake CRB Board Jumpers Description Jumper J6LB Description Clear CMOS (1-2: Normal, 2-3: Clear CMOS) RTC Reset (1-2: Normal, 2-3: Clear) Config /Recovery (1-2: Normal, 2-3: Configure, jumper removed – recovery) Manufacturing mode (enable if jumper plug-in) Default Position 1-2 1-2 1-2 Empty J115LB J7LB J4LB/J10LB 20 2. 8. 2 USB 2. 0 Front Panel There are 4 USB 2. 0 Front Panel can be found in the development kits board. USB front panel is label as J14LB, J15LB, J16LB and J1FW on the boards. Refer to Figure 2-13 for U1FW. Pin Number 1 2 3 4 5 6 7 8 9 10 Definition 5V 5V USB DxUSB DyUSB Dx+ USB Dy+ GND GND No pin No connect Table 2-4 USB Front Panel 2. 8. 3 1394a Header 1394a solution on the PCIe bus. Single 1394a port on the back panel; refer to figure 2. 9 for the back panel 1394a locations. There’s another header supporting 1394a port, which is shown in figure 2-13. Each IEEE 1394a connector provides one IEEE 1394a port. 21 Pin Number 1 2 3 4 5 6 7 8 9 10 Definition TP A+ TP AGround Ground TP B+ TP B+12V DC +12V DC No Pin Ground Table 2-5 1394a Header USB front panel J24LB 1394a Header Figure 2-13 Location for 1394a Header and USB front panel. 22 2. 9 SPI Removal / Installation Technique When removing or installing the SPI device care must be taken to avoid damage to the SPI socket. The cap is constructed of plastic and can easily be damaged. 2. 9. 1 SPI Device Installation Suggested tooling to use for install and removal other basic FA equipment may be needed but not necessary. Figure 2-14 : Pick and tweezer i. Door identified prior to install or removal of SPI device Figure 2-15 : Door 1 and 2 ii. Using pick, gently push up from under the lip to open door 1. Figure 2-16 : Opening door 1 23 iii. Follow the same steps as opening door 1 for door 2 Figure 2-17 : Opening door 2 iv. [. . . ] Disable : IGD is disabled regardless of card detection And the primary video device option 41 Memory Remap feature Enabled : allow remapping of the overlapped PCI memory above the total physical memory Disabled : do not allow remapping of memory Flex Memory Mode Enabled : Flex mode channels interleaved when possible Disabled : Non flex mode channels stacked DRAM frequency Select the DRAM frequency Note : Setting auto, the DRAM frequency will auto adjusted Configure DRAM time by SPD Enable or disable Dynamic ODT Power cycling is required after changing this option Write levelization Enabled or disabled write levelization ( DDR3 only ) Memory hole Reserve place in the memory. Select the amount that to be reserve. T2 Dispatch Enable T2 dispatch for increase memory performance Auto PCI MMIO Allocation Enabled or disabled the auto PCI MMIO Allocation Note : MMIO stands for memory mapped input output TSEG Allocation Select the i. iv. type of TSEG allocation disabled enabled, 1MB enabled, 2MB enabled, 8MB Video function configuration i. DVMT/Fixed memory Boot displays device Flat panel type Backlight control support BIA Control TV standard Fixed or DVMT mode Select the boot displays device Select the flat panel type from type 1~type 9 Select the backlight control support vi. [. . . ]