User manual INTEL INTEL PENTIUM U5000 DATASHEET 2010

[. . . ] Intel® Pentium® P6000 and U5000 Mobile Processor Series Datasheet This is volume 1 of 2. Refer to Document 322813 for Volume 2 June 2010 Document Number: 323873-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Legal Lines and Disclaimers UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. [. . . ] Under no circumstances should this value be altered from the default register value after reset of the processor. Altering this MSR value may result in unpredictable behavior. 5. 1. 2 Intel Graphics Dynamic Frequency Thermal Design Considerations and Specifications When designing a thermal solution for Intel Graphics Dynamic frequency enabled processor: · Both component TDPs as well as extreme thermal power levels for the processor core and integrated graphics and memory controller must be considered. · Note that the processor can consume close to its maximum thermal power limit more frequently, and for prolonged periods of time. · One must ensure that the component Tj, max limits are not exceeded when either component is operating at its extreme thermal power limit. There are two "extreme" design points: · The processor core operating at maximum thermal power level (which is greater than its component TDP) and the integrated graphics and memory controller operating at its minimum thermal power. · The integrated graphics operates at its maximum thermal power level, while the processor core consumes the remaining thermal power budget. In both cases, the combined component thermal power will not exceed the total MCP package power limit. The design approach accommodating two extreme power levels is referred to as a "two-point" design. The following notes apply to Table 5-17 and Table 5-19. Note 1 Definition The component TDPs given are not the maximum power the components can generate. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained periods of time. A range of power is to be expected among the components due to the natural variation in the manufacturing process. Nevertheless, the individual component powers are not to exceed the component TDPs specified. Concurrent package power refers to the actual power consumed by the package while TDP applications are running simultaneously by the processor core and the integrated graphics controller. An example of this could be the processor core running a Prime95* application, and the integrated graphics core running a Star Wars: Jedi Knight* menu simultaneously. The thermal solution needs to ensure that the temperatures of both components do not exceed the maximum junction temperature (Tj, max) limit, as measured by the DTS and the critical temperature bit. Please refer to processor Specification Update for Tjmax value per sku. 2 3 4 Datasheet 53 Thermal Management Note 5 Definition Processor core and integrated graphics and memory controller junction temperatures are monitored by their respective DTS. A DTS outputs a temperature relative to the maximum supported junction temperature. The error associated with DTS measurements will not exceed ±5°C within the operating range. The power supply to the processor core and the integrated graphics /Memory core should be designed as per Intel's guidelines. Processor core currents is monitored by IMON VR feedback (ISENSE) and calculated using a moving average method. Error associated with power monitoring will depend upon individual VR design. A thermal solution for an power sharing enabled system needs to ensure that the Tj limit is not exceeded while operating under the two extreme power conditions between the processor core and the integrated graphics and memory controller components. For power sharing designs it is recommended to establish the full cooling capability within 10°C of the Tj, max specifications. Some processors may have a different Tj max value, please refer to the processor Specification Update for details. In rare occasions the specified maximum power limits may be violated when the package is not at a thermally constrained environment Tj, min =0 deg While running intensive graphical and computational workloads simultaneously the concurrent package power may exceed specified limits in exceptional occasions. [. . . ] I/O Table 8-49. rPGA988A Processor Pin List by Pin Number Pin Number AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AN1 AN2 AN3 AN4 Pin Name SB_DQ[42] SA_DM[5] VSS SA_DQ[52] SA_DQ[49] VSS SA_DQ[56] SA_DQ[58] VSS VTTPWRGOOD VAXG VSS VAXG VAXG VSS VAXG GFX_VID[0] GFX_VID[4] GFX_IMON VSS TAPPWRGOOD VSS CFG[1] VSS CFG[0] CFG[5] CFG[7] CSC[2]/VID[5] PROC_DPRSLPV R VID[6] SM_RCOMP[2] SB_DQ[43] SB_DQ[53] SB_DQ[52] Buffer Type DDR3 DDR3 GND DDR3 DDR3 GND DDR3 DDR3 GND Async CMOS REF GND REF REF GND REF CMOS CMOS Analog GND Async CMOS GND CMOS GND CMOS CMOS CMOS CMOS CMOS CMOS Analog DDR3 DDR3 DDR3 I I I I/O O O I I/O I/O I/O I O O O I I I/O I/O I/O I/O Dir. I/O O 113 Datasheet Processor Pin and Signal Information Table 8-49. rPGA988A Processor Pin List by Pin Number Pin Number AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AP1 AP2 Pin Name SB_DQ[49] SB_DQ[51] SB_DQ[56] SA_DQ[48] SA_DQ[53] SA_DM[6] SA_DQS[6] SA_DQ[57] SA_DM[7] VCCPWRGOOD_ 1 PM_EXT_TS#[0 ] VAXG VSS VAXG VAXG VSS VAXG GFX_VID[2] VSS GFX_VID[6] DBR# PROCHOT# VCCPWRGOOD_ 0 TCK CFG[6] CFG[12] VSS CFG[13] PSI# VSS ISENSE RSVD_NCTF VSS GND Async GTL Async CMOS CMOS CMOS CMOS GND CMOS Async CMOS GND Analog I I O Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Async CMOS CMOS REF GND REF REF GND REF CMOS GND CMOS O O I/O I I I I O Dir. I/O I/O I/O I/O I/O O I/O I/O O I I Table 8-49. rPGA988A Processor Pin List by Pin Number Pin Number AP3 AP4 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 AP35 Pin Name SB_DQ[48] VSS VSS SB_DQS[6] SB_DQ[57] VSS SB_DQ[58] SB_DQ[61] VSS SA_DQS#[6] SA_DQ[55] VSS SA_DQ[63] PM_EXT_TS#[1 ] VAXG VSS VAXG VAXG VSS VAXG GFX_VID[1] GFX_VID[3] GFX_VID[5] RSVD RESET_OBS# PREQ# TMS TDO_M RSVD CFG[2] RSVD RSVD VSS RSVD_NCTF GND CMOS I Async CMOS Async GTL CMOS CMOS O I I O Buffer Type DDR3 GND GND DDR3 DDR3 GND DDR3 DDR3 GND DDR3 DDR3 GND DDR3 CMOS REF GND REF REF GND REF CMOS CMOS CMOS O O O I/O I I/O I/O I/O I/O I/O I/O Dir. I/O Datasheet 114 Processor Pin and Signal Information Table 8-49. rPGA988A Processor Pin List by Pin Number Pin Number AR1 AR2 AR3 AR4 AR5 AR6 AR7 AR8 AR9 AR10 AR11 AR12 AR13 AR14 AR15 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR25 AR26 AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AT1 Pin Name RSVD_NCTF RSVD_NCTF VSS SB_DM[6] SB_DQS#[6] VSS SB_DQS[7] SB_DQS#[7] VSS SB_DQ[62] SA_DQ[50] VSS SA_DQS[7] SA_DQ[62] VSS VAXG VSS VAXG VAXG VSS VAXG VAXG_SENSE VSS VSS GFX_VR_EN VSS TDO VSS TDI_M BCLK_ITP VSS RSVD RSVD VSS_NCTF RSVD_NCTF VSS_NCTF GND DDR3 DDR3 GND DDR3 DDR3 GND DDR3 DDR3 GND DDR3 DDR3 GND REF GND REF REF GND REF Analog GND GND CMOS GND CMOS GND CMOS DIFF CLK GND I O O O O I/O I/O I/O I/O I/O I/O O I/O Buffer Type Dir. Table 8-49. rPGA988A Processor Pin List by Pin Number Pin Number AT2 AT3 AT4 AT5 AT6 AT7 AT8 AT9 AT10 AT11 AT12 AT13 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AT33 AT34 AT35 Pin Name RSVD_TP RSVD_NCTF SB_DQ[50] SB_DQ[54] SB_DQ[55] SB_DQ[60] SB_DM[7] SB_DQ[59] SB_DQ[63] SA_DQ[54] SA_DQ[60] SA_DQS#[7] SA_DQ[59] PECI VAXG VSS VAXG VAXG VSS VAXG VSSAXG_SENS E COMP3 COMP2 GFX_DPRSLPVR COMP0 TRST# PRDY# TDI BCLK_ITP# RSVD RSVD RSVD_NCTF RSVD_NCTF VSS_NCTF DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Async REF GND REF REF GND REF Analog Analog Analog CMOS Analog CMOS Async GTL CMOS DIFF CLK O I I O I I O I O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O Buffer Type Dir. 115 Datasheet Processor Pin and Signal Information Table 8-49. rPGA988A Processor Pin List by Pin Number Pin Number B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 C1 Pin Name VSS_NCTF VSS_NCTF SB_DQ[3] VSS SB_DQ[0] VSS SA_DQ[13] VSS SA_DM[0] SA_DQ[4] VSS VTT0 VSS VTT0 VTT_SENSE BCLK# VSS VSS RSVD RSVD VSS DMI_RX#[2] DMI_RX[2] DMI_RX[0] VSS PEG_ICOMPI PEG_RCOMPO PEG_RX#[13] PEG_RX[14] PEG_RX#[14] VSS PEG_RX#[11] PEG_RX[9] VSS_NCTF RSVD_NCTF RSVD_NCTF GND DMI DMI DMI GND Analog Analog PCIe PCIe PCIe GND PCIe PCIe I I I I I I I I I I DDR3 GND DDR3 GND DDR3 GND DDR3 DDR3 GND REF GND REF Analog DIFF CLK GND GND O I O I/O I/O I/O I/O Buffer Type Dir. Table 8-49. rPGA988A Processor Pin List by Pin Number Pin Number C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 D1 D2 Pin Name SB_DQ[12] SB_DQ[2] SB_DQ[7] SB_DQS[0] SA_DQ[15] SA_DQ[2] SA_DQS[0] SA_DQS#[0] SA_DQ[1] VTT0 VTT0 VTT0 VTT0 RSVD VSS FDI_INT FDI_TX[3] VSS VSS FDI_TX[1] VSS DMI_RX#[1] VSS PEG_TX[15] PEG_TX#[15] PEG_TX[14] VSS VSS PEG_RX[12] PEG_RX#[12] VSS PEG_RX#[9] VSS RSVD_NCTF SB_DQ[8] SB_DQ[9] DDR3 DDR3 I/O I/O GND CMOS FDI GND GND FDI GND DMI GND PCIe PCIe PCIe GND GND PCIe PCIe GND PCIe GND I I I O O O I O I O Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 REF REF REF REF Dir. [. . . ]