User manual INTEL INTEL PENTIUM 4 PROCESSOR IN 478-PIN PACKAGE DESIGN GUIDE UPDATE 2004

[. . . ] No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. [. . . ] This Design Guide Update may reference other documents listed in the following Affected Documents/Related Documents table. This document is a compilation of updates to the general design considerations; schematic, layout, and routing updates; and documentation changes. This document is intended for hardware system manufacturers and for software developers of applications, operating systems, and tools. The design guide (and this design guide update) is primarily targeted at the PC market segment and was first published in 2002. Those using this design guide and update should check for device availability before designing in any of the components included in this document. Information types defined in the Nomenclature section of this document are consolidated into the public design guide update document when the public design guide document is first published. This design guide update document contains a complete list of all known information types. Affected Documents Document Title Intel® Pentium® 4 Processor in 478-pin Package and Intel® 845 Chipset Platform for SDR Design Guide, January 2002 Document Number 298354-002 Related Documents Document Title Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR Datasheet, January 2002 Intel® 82801BA (ICH2) I/O Controller Hub Datasheet Document Number 290725-002 290687-002 Nomenclature General Design Considerations include system level considerations that the system designer should account for when developing hardware or software products using the Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR. Schematic, Layout, and Routing Updates include suggested changes to the current published schematics or layout, including typos, errors, or omissions from the current published documents. Documentation Changes include suggested changes to the current published design guide not including the above. Design Guide Update 5 Preface R Codes Used in Summary Table Doc: Document change or update that will be implemented. Shaded: This item is either new or modified from the previous version of the document. NO. Plans GENERAL DESIGN CONSIDERATIONS There are no General Design Consideration changes in this Design Guide Update revision. NO. 1 Plans Doc SCHEMATIC, LAYOUT, AND ROUTING UPDATES Schematic change to the 82845 MCH HSWING Circuit NO. 1 2 3 4 5 6 7 8 Plans Doc Doc Doc Doc Doc Doc Doc Doc DOCUMENTATION CHANGES Change Section 12. 4. 2, 3. 3V/V5REF Sequencing Change Section 14. 8, Power and Ground, V5REF_SUS Replace Figure 118, Intel® 845 Chipset Platform Using PC133 SDRAM System Memory Power Delivery Map Add Section 4. 6. 7, Electrostatic Discharge Platform Recommendations Change Table 3, System Bus Routing Summary for the Processor Add Section 13. 2, Intel® Boxed Processor Mechanical Keep-Outs Add Section 15. 1. 3, Intel® Boxed Processor Mechanical Keep-Outs Revise Section 14. 1, Schematic Checklist, Host Interface, PWRGOOD 6 Design Guide Update General Design Considerations R General Design Considerations There are no General Design Considerations in this Design Guide Update revision. Design Guide Update 7 General Design Considerations R This page is intentionally left blank. 8 Design Guide Update Schematic, Layout, and Routing Updates R Schematic, Layout, and Routing Updates 1. Schematic Change to the 82845SDR MCH HSWING Circuit Reference Appendix A, Customer Reference Board Schematics, of the Intel® Pentium® 4 Processor in 478-Pin Package and Intel® 845 Chipset Platform for SDR Design Guide, 298354002, dated January 2002. Sheet 11 of the "Intel® 845 SDR Schematics Rev 1. 3" contains a circuit at grid location C-7. Capacitor C5D6 is shown as a series capacitor between VCCP and the HSWING output. It should connect the HSWING output of this circuit to GND so that resistor R5D5 and capacitor C5D6 are in parallel. R5D7 Sheets 62, 61, 60, 59, 46, 18, 17, 11, 10, 9, 7, 6, 5 VCCP IN R5D5 C5D6 HSWING OUT Sheet 9 Design Guide Update 9 Schematic, Layout, and Routing Updates R This page is intentionally left blank. 10 Design Guide Update Documentation Changes R Documentation Changes 1. Changed: Change Section 12. 4. 2, 3. 3V/V5REF Sequencing Change the third paragraph to read: As an additional consideration, during suspend, the only signals that are 5 V tolerant capable are USB OC:[3:0]#. [. . . ] The board designer should fill the entire I/O area along the board edge. The spacing from the ground fill to other shapes/traces should be at least 20 mils. It is recommended that these ground fill areas be connected to two chassis mounting holes (as seen in Figure 2). This will allow ESD current to travel to the chassis instead of the board. [. . . ]