User manual INTEL CELERON 1.10 GHZ

[. . . ] Intel® Celeron® Processor up to 1. 10 GHz Datasheet s s s s s s s Available at 1. 10 GHz, 1 GHz, 950 MHz, 900 MHz, 850 MHz, 800 MHz, 766 MHz, 733 MHz, 700 MHz, 667 MHz, 633 MHz, 600 MHz, 566 MHz, 533 MHz, 533A MHz, 500 MHz, 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, and 300A MHz core frequencies with 128 KB level-two cache (on die); 300 MHz and 266 MHz core frequencies without level-two cache. Intel's latest Celeron® processors in the FC-PGA/FC-PGA2 package are manufactured using the advanced 0. 18 micron technology. Binary compatible with applications running on previous members of the Intel microprocessor line. Specifically designed for uni-processor based Value PC systems, with the capabilities of MMXTM technology. [. . . ] System Bus AC Specifications (TAP Connection)1, 2, 3 T# Parameter T30: TCK Frequency T31: TCK Period T32: TCK High Time T33: TCK Low Time T34: TCK Rise Time 60. 0 25. 0 25. 0 5. 0 Min Max 16. 667 Unit MHz ns ns ns ns 3 3 3 3 VREF + 0. 200 V, 10 VREF ­ 0. 200 V, 10 (VREF ­ 0. 200 V) ­ (VREF + 0. 200 V), 4, 10 T35: TCK Fall Time T36: TRST# Pulse Width T37: TDI, TMS Setup Time T38: TDI, TMS Hold Time T39: TDO Valid Delay T40: TDO Float Delay T41: All Non-Test Outputs Valid Delay T42: All Non-Test Inputs Setup Time T43: All Non-Test Inputs Setup Time T44: All Non-Test Inputs Hold Time 5. 0 13. 0 2. 0 40. 0 5. 0 14. 0 1. 0 10. 0 25. 0 25. 0 25. 0 5. 0 ns ns ns ns ns ns ns ns ns ns 3 10 9 9 9 9 9 9 9 9 (VREF + 0. 200 V) ­ (VREF ­ 0. 200 V), 4, 10 Asynchronous, 10 5 5 6, 7 6, 7, 10 6, 8, 9 6, 8, 9, 10 5, 8, 9 5, 8, 9 Figure Notes NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processors frequencies. All AC timings for the TAP signals are referenced to the TCK rising edge at 0. 75 V at the processor pins. All TAP signal timings (TMS, TDI, etc. ) are referenced at 0. 75 V at the processor pins. These specifications are tested during manufacturing, unless otherwise noted. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16. 667 MHz. Valid delay timing for this signal is specified to 1. 5 V (1. 25 V for AGTL platforms). Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These timings correspond to the response of these signals due to TAP operations. During Debug Port operation, use the normal specified timings rather than the TAP signal timings. Specified by design characterization. Datasheet 47 Intel® Celeron® Processor up to 1. 10 GHz Note: For Figure 3 through Figure 10, the following apply: 1. Figure 3 through Figure 10 are to be used in conjunction with Table 9 through Table 26. All AC timings for the AGTL+ signals at the processor edge fingers are referenced to the BCLK rising edge at 0. 50 V. This reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1. 25 V. All AGTL+ signal timings (address bus, data bus, etc. ) are referenced at 1. 00 V at the processor edge fingers. All AC timings for the AGTL+ signals at the processor core pins are referenced to the BCLK rising edge at 1. 25 V. All AGTL+ signal timings (address bus, data bus, etc. ) are referenced at 1. 00 V at the processor core pins. All AC timings for the CMOS signals at the processor edge fingers are referenced to the BCLK rising edge at 0. 50 V. This reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1. 25 V. All CMOS signal timings (compatibility signals, etc. ) are referenced at 1. 25 V at the processor edge fingers. All AC timings for the APIC I/O signals at the processor edge fingers are referenced to the PICCLK rising edge at: 0. 7 V for S. E. P. and PPGA packages and 0. 75 V for the FC-PGA/FC-PGA2 packages at the processor edge fingers. [. . . ] Intel Celeron processors require this signal to be driven low during power on Reset. A 680 ohm resistor is the suggested value for a pull down resistor on TRST#. The 2. 5 V must be provided to the VCC2. 5 input and 1. 5 V must be provided to the VCC1. 5 input. The processor re-routes the 1. 5 V input to the VCCCMOS output via the package. [. . . ]