User manual INTEL 852GM DESIGN GUIDE

[. . . ] R Intel® 852GM Chipset Platform Design Guide For Use with the Mobile Intel® Pentium® 4 Processor-M, Mobile Intel® Celeron® Processor on . 13 Micron Process in the 478-Pin Package, and Intel® Celeron® M Processor January 2005 Document Number: 252338-003 R Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. [. . . ] There should be a minimum of 20 mils of spacing to nonDDR related signals. Command signals should be routed on inner layers with minimized external trace lengths. Intel® 852GM Chipset Platform Design Guide 111 System Memory Design Guidelines (DDR-SDRAM) R 7. 3. 6. 5. Command Topology 2 Routing Guidelines Table 42. Command Topology 2 Routing Guidelines Parameter Routing Guidelines Signal Group Motherboard Topology Reference Plane Characteristic Trace Impedance (Zo) Nominal Trace Width Minimum Spacing to Trace Width Ratio Minimum Isolation Spacing to non-DDR Signals Package Length P1 Trace Length L1 ­ GMCH Command Signal Ball to Series Resistor Pad Trace Length L2 ­ Series Resistor Pad to First SO-DIMM Pad Trace Length L3 ­ Series Resistor Pad to Second SODIMM Pad Trace Length L2 + L3 ­ Total SO-DIMM to SO-DIMM spacing Trace Length L4 ­ Second SO-DIMM Pad to Parallel Resistor Pad Series Termination Resistor (Rs) Parallel Termination Resistor (Rt) Maximum Recommended Motherboard Via Count Per Signal SMA[12:6, 3, 0], SBA[1:0], SRAS#, SCAS#, SWE# Branched T with Parallel Termination Ground Referenced 55 ± 15% Inner layers: 4 mils Outer layers: 5 mils 2 to 1 (e. g. 8 mil space to 4 mil trace) 20 mils 500 mils ± 250 mils (See Table 44 for exact package length. ) Min = 0. 5 inches Max = 4. 0 inches Max = 1. 0 inches Max = 2. 0 inches Max = 3. 0 inches Max = 1. 0 inches 10 ± 5% 56 ± 5% 6 CMD to SCK/SCK# [5:0] Length Matching Requirements See length matching Section 7. 3. 6. 6 and Figure 56 for details. NOTES: 1. Recommended resistor values and trace lengths may change in a later revision of the design guide. Power distribution vias from Rt to Vtt are not included in this count. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching requirements. It is possible to route using three vias if one via is shared that connects to the SO-DIMM0 pad and series termination resistor, if a via is shared that connects L1 to series termination and if one via is shared that connects to the SO-DIMM1 pad and parallel termination resistor. 112 Intel® 852GM Chipset Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) R 7. 3. 6. 6. Command Topology 2 Length Matching Requirements The routed length of the command signals, between the GMCH package ball and the SO-DIMM must be within the range defined below, with respect to the associated clock reference length. Refer to Figure 55 for a definition of the various motherboard trace segments. The length of trace from the SO-DIMM to the termination resistor need not be length matched. Refer to Section 7. 1 for more details on length matching requirements. Length range formula for SO-DIMM0: X0 = SCK/SCLK#[2:0] total reference length, including package length. Y0 = CMD signal total length = GMCH package + L1 + L2, as shown in Figure 55, where: ( X0 ­ 1. 0" ) Y0 ( X0 + 2. 0" ) Length range formula for SO-DIMM1: X2 = SCK/SCLK#[5:3] total reference length, including package length. Y2 = CMD signal total length = GMCH package length + L1 + L3, as shown in Figure 55, where: ( X1 ­ 1. 0" ) Y1 ( X1 + 2. 0" ) No length matching is required from SO-DIMM1 to the termination resistor. Figure 56 on the following page depicts the length matching requirements between the command signals and clock. A nominal CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 7. 2 for more details on package length compensation. Intel® 852GM Chipset Platform Design Guide 113 System Memory Design Guidelines (DDR-SDRAM) R Figure 56. Topology 2 Command Signal to Clock Trace Length Matching Diagram SO-DIMM0 GMCH Package SMAA[12:6, 3, 0] SBA[1:0], SRAS#, SCAS#, SWE# CMD Length = Y0 GMCH Die SCK[2:0] SCK#[2:0] (X0 ­ 1. 0") <= Y0 <= (X0 + 2. 0") Clock Reference Length = X0 Note: All lengths are measured from MCH die pad to SO-DIMM connector pad. SO-DIMM0 SO-DIMM1 GMCH Package SMAA[12:6, 3, 0] SBA[1:0], SRAS#, SCAS#, SWE# CMD Length = Y1 GMCH Die SCK[5:3] SCK#[5:3] (X1 ­1. 0") <= Y1 <= (X1 +2. 0") Clock Ref Length = X1 Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. 114 Intel® 852GM Chipset Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) R 7. 3. 6. 7. Command Topology 2 Routing Example Figure 57 is an example of a board routing for the Command signal group. Figure 57. Example of Command Signal Group From 852GM Command Signals Intel® 852GM Chipset Platform Design Guide 115 System Memory Design Guidelines (DDR-SDRAM) R 7. 3. 6. 8. Command Topology 3 This topology is recommended when the SO-DIMMS are too close together for the series resistor to be placed between connectors. In this topology the series resistors are placed behind the second SODIMM. It is suggested that the parallel termination be placed on both sides of the board to simplify routing and minimize trace lengths. All internal and external signals should be ground referenced to keep the path of the return current continuous. [. . . ] R1IN R2IN R3IN R4IN R5IN T1OUT T2OUT T3OUT 4 5 6 7 8 SERBUF_CTSA SERBUF_RIA SERBUF_SINA# SERBUF_DSRA SERBUF_DCDA V3 SERBUF_VC7A1 0. 1UF 34 34 34 V+ 27 SERBUF_V+ C8A4 C7M1 C7M2 0. 1UF NO_STUFF_0. 1UF NO_STUFF_10UF 26 VCC 2 19, 21, 37 PM_RI# 3 SERBUF_C1+ 28 C8A3 0. 1UF SERBUF_C1- 24 1 2 Q8H2 BSS138 SERBUF_C2+ C7A3 0. 1UF SERBUF_C2SER_RIA 34 SER_CTSA# 34 SER_RIA# 34 SER_SINA 34 SER_DSRA# 34 SER_DCDA# 34 SER_DTRA# 34 SER_SOUTA 34 SER_RTSA# 2 20 19 18 17 16 15 14 13 12 23 22 21 1 11 2 NO_STUFF_HSDL-3600#017 Caps must be placed as close as possible to pins 1, 2 SERIAL PORT 1 4 3 4 8 5 6 5 60OHM@100MHZ SERPRT_DCDA FB1A1A SERPRT_DSRA FB1A2D SERPRT_SINA# FB1A2C FB1A1D SERPRT_RTSA J2A1B 26 31 27 32 28 33 29 34 30 50 51 52 53 54 55 1 9 SERBUF_DTRA 10 SERBUF_SOUTA# 11 SERBUF_RTSA 3 1 2 2 6 8 7 7 60OHM@100MHZ FB1A1C SERPRT_SOUTA# FB1A2A SERPRT_CTSA FB1A1B SERPRT_DTRA FB1A2B SERPRT_RIA 8 1 +V3. 3S R8A1 1K 19 SER_EN SER_ON GND 25 CONN, MISC, 49P, D-SUB, 3-IN-1 Title Size A Floppy, Parallel, Serial, and IR Ports Project: Intel 852GM CRB D Document Number A# 35 of E Rev 59 A B C A B C D E +V5_PS2 KBC_SCANOUT[15:0] 32 CBTD has integrated diode for 5V to 3. 3V voltage translation 2 4 6 8 10 12 14 16 18 20 22 24 KBC_SCANOUT1 KBC_SCANOUT3 KBC_SCANOUT5 KBC_SCANOUT7 KBC_SCANOUT9 KBC_SCANOUT11 KBC_SCANOUT13 KBC_SCANOUT15 KBC_SCANIN1 KBC_SCANIN3 KBC_SCANIN5 KBC_SCANIN7 J9D1 KBC_SCANOUT0 KBC_SCANOUT2 KBC_SCANOUT4 KBC_SCANOUT6 KBC_SCANOUT8 KBC_SCANOUT10 KBC_SCANOUT12 KBC_SCANOUT14 KBC_SCANIN0 KBC_SCANIN2 KBC_SCANIN4 KBC_SCANIN6 1 3 5 7 9 11 13 15 17 19 21 23 U8A3 32 32 32 32 32 KBC_GP_DATA KBC_GP_CLK KBC_MOUSE_DATA KBC_MOUSE_CLK KBC_KB_DATA 3 4 7 8 11 14 17 18 21 22 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 C8A6 0. 1UF 4 4 VCC 1B1 1B2 1B3 1B4 1B5 24 2 5 6 9 10 GP_DATA GP_CLK MOUSE_DATA MOUSE_CLK KBD_DATA 32 KBC_KB_CLK 18 H_A20GATE NO_STUFF_24Pin_ZIF-HDR Scan Matrix Key Board KBC_SCANIN[7:0] +V5_PS2 +V5_PS2 32 KBD_CLK 2B1 15 2B2 16 19 2B3 2B4 20 2B5 23 OE#_PS2 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 35, 38. . 40, 42, 44, 48 1 1OE# 13 2OE# GND 12 SN74CBTD3384 R8A5 100 3 RP8G2C 6 8. 2K KBC_A20GATE 32, 37 +V3. 3S 5, 15, 19. . 23, 27. . 29, 32, 37. . 39, 44, 48 2 3 +V3. 3ALWAYS 10K 10K 10K 10K 10K 10K 10K 10K 3 2 RP1B1B 4. 7K PS2_PWR_L +1 GP_CLK FB1A9 60ohm@100MHz 1 2 7 F1A1 1. 1A +V5_PS2 1 RP8G1D RP8H6A RP8H6B RP8H6D RP8H7A RP9G1B RP9G1C 4 1 2 4 1 2 3 R9A2 5 8 7 5 8 7 6 2 RP1B2A 4. 7K FB1A4 60ohm@100MH z 1 2 8 SMC_EXTSMI# 19, 32, 34, 37 SMC_RUNTIME_SCI# 19, 32, 37 SMC_WAKE_SCI# 19, 32, 37 PM_BATLOW# 19, 32, 37 SMB_SB_DATA 32, 37, 44 SMB_SB_CLK 32, 37, 44 SMB_SB_ALRT# 32, 37, 44 DOCK_INTR# 24, 32, 37 CP1A1B 47PF 7 1 FB1A6 31Ohm@100MH z 2 L_GPDATA GP_DATA +V5_PS2 +V5_PS2 2 L_PS2_PWR 4 RP1B2B 4. 7K J1A1 L_GPCLK L_KBD_CLK 7 642 5 13 14 15 10 12 11 L_MOUSE_CLK +V5_PS2 3 9 DUAL_PS2 L_MOUSE_DATA 1 8 7 +V5_PS2 C1B1 22UF If a PS/2 "breakout" connector is used, the keyboard PS/2 connector can be used for both a PS/2 keyboard and a second PS/2 mouse. Otherwise, the keyboard PS/2 connector will only support a PS/2 keyboard. 1 C1A2 47pF +V5_PS2 R1B1 KBD_DATA 0. 01_1% +V5 20. . 23, 27, 37, 42. . 44 2 2 KBD_CLK RP1B2D 4. 7K FB1A8 60ohm@100MHz 1 2 3 CP1A1C 47PF 1 3 16 17 FB1A3 60ohm@100MH z L_KBD_DATA 1 2 5 C1A1 47pF +V5_PS2 6 C1B2 0. 1UF RP1B2C 4. 7K FB1A7 60ohm@100MHz 1 2 4 CP1A1D 47PF 6 RP1B1A 4. 7K FB1A5 60ohm@100MHz 2 8 MOUSE_DATA 1 CP1A1A 47PF 1 MOUSE_CLK 1 5 8 Title Size A Keyboard and Mouse Connectors Project: Intel 852GM CRB D Document Number A# 36 of E Rev 59 A B C A B C D E 15, 17, 23, 27, 44 +V12S LPC POWERED ON SUSPEND RAIL FOR ADD-IN H8 CARD J3H1 4, 18 H_PWRGD 18, 21 SM_INTRUDER# 19, 21, 35 PM_RI# 3, 7, 18 H_DPSLP# 18, 21 SMB_ALERT# 3, 18 H_NMI 3, 18 H_SMI# 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 2X8_HDR H_INIT# 3, 18 H_INTR 3, 18 BUF_PCI_RST# +V5 R4169_D LPC Debug Slot +V3. 3_LPCSLOT 15, 17, 23, 27, 44 J8F1 4 +V3. 3_LPCSLOT +V12S 20. . 23, 2 18, 22. . 24, 26, 31, 32, 34 R3H3 1K H_STPCLK# 3, 18 H_CPUSLP# 3, 18 19, 33 SUS_CLK 5, 15, 19. . 23, 27. . 29, 32, 36, 38, 39, 44, 48 +V3. 3ALWAYS 18, 32 H_RCIN# 32, 36 KBC_A20GATE 19, 32, 34, 36 SMC_EXTSMI# +V5_LPCSLOT B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 12V1 SUSCLK GND1 LREQ VCC3_1 LCNTL0 GND3 LDC LD5 GND4 LD3 LD1 GND6 3V_STBY LPS KBRESTE# A20GATE# GND8 LSMI# 12V2 A1 NEG_12V A2 GND2 A3 BP_CLK A4 VCC3_2 A5 LCNTL1 A6 GND5 A7 LD6 A8 LD4 A9 GND7 A10 +V5_LPCSLOT LD2 A11 LD0 A12 A13 VCC5_2 SCLK A14 GND10 A15 INT_SERIRQ 18, 22. . 24, 32, 34 SERIRQ A16 PM_CLKRUN# 19, 21. . 24, 32, 34 CLKRUN# A17 GND12 A18 5, 15, 19. . 23, 27. . 29, 32, 36, 38, 39, 44, 48 +V3. 3ALWAYS LINK_ON A19 KEY R8G9 VCC5_3 LDRQ0# GND14 LAD3 LAD1 GND15 PCICLK LPCPD# GND16 PME# VCC3_4 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 10K LPC_DRQ#0 19 LPC_AD3 19, 31. . 34 LPC_AD1 19, 31. . 34 CLK_LPCPCI 6 PM_SUS_STAT# 19, 32, 34, 48 PCI_PME# 15, 18, 22, 23 4 20, 21 19. . 22, 24 +V3. 3S_ICH +V3. 3ALWAYS_ICH R7J3 R7J4 10K 4. 7K J7J1 19 ICH_GPIO7 18, 21. . 23 INT_PIRQH# 19 ICH_MFG_MODE 15, 18, 22, 23 PCI_PME# 1 3 5 7 9 2 4 6 8 10 IDE_PATADET 19, 26 IDE_SATADET 19, 26 2X5-Header ICH4-M Testpoint Header J9J1 6, 19, 39, 40 6, 19, 38, 44 19, 48 3, 19 39 PM_STPCPU# PM_SLP_S1# PM_C3_STAT# PM_CPUPERF# VR_PWRGD 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 PM_STPPCI# 6, 19 INT_IRQ14 18, 21, 26 INT_IRQ15 18, 21, 26 AGP_SUSPEND# 19 PM_CLKRUN# 19, 21. . 24, 32, 34 PM_SLP_S4# 19, 20, 32, 38, 43, 44 3 3 19 LPC_DRQ#1 19, 31. . 34 LPC_FRAME# 19, 31. . 34 LPC_AD2 19, 31. . 34 LPC_AD0 6 CLK_LPC14 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 VCC5_1 LDRQ1# LFRAME1# GND9 LAD2 LAD0 GND11 PCIRST# GND13 OSC VCC3_3 60Pin_CardCon 2X8_HDR LPC_RST# Layout Note: Line up LPC slot with PCI Slot 3 R9G4 0 J2J2 27, 34 IDE_SPWR_EN# 1 3 5 7 2 4 6 8 FWH_WP# 19, 31 FWH_TBL# 19, 31 22, 23, 32 PCI_GATED_RST# R9G3 NO_STUFF_0 BUF_PCI_RST# 18, 22. . 24, 26, 31, 32, 34 8Pin HDR SIO Sidebands TEST HEADER J9D2 2 J2J1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 SMC_RUNTIME_SCI# 19, 32, 36 SMC_WAKE_SCI# 19, 32, 36 FAN_ON 32, 38 SMB_THRM_CLK 5, 32 SMB_THRM_DATA 5, 32 SMB_SB_CLK 32, 36, 44 SMB_SB_DATA 32, 36, 44 SMB_SB_ALRT# 32, 36, 44 PM_BATLOW# 19, 32, 36 19, 32, 34, 36 SMC_EXTSMI# 19, 38 PM_SLP_S5# 19, 39, 40 PM_DPRSLPVR 1 3 5 7 2 4 6 8 DELAYED_VR_PWRGD PM_SUS_CLK 15, 19 PM_GMUXSEL 19 19, 40 2 5, 19, 21, 32 19, 32 32, 44 32, 39, 42 19, 21, 25, 32, 39 PM_THRM# PM_PWRBTN# SMC_ONOFF# VR_ON PM_PWROK 19, 21, 32 PM_RSMRST # 32, 44 AC_PRESENT# 19, 25, 32, 38, 43, 44 PM_SLP_S3# 44, 48 GATED_SMC_SHUTDOWN 32 BAT_SUSPEND 32 SMC_RSTGATE# 24, 32, 36 DOCK_INTR# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 8Pin HDR NO STUFF SMB_SC_INT# 32 GROUND HEADERS J9J4 1 2 1 J7E1 2 1 J7F2 2 1 J1H6 2 1 J2A2 2 15x2_HDR SMC Sidebands for LPC Power Management J9J3 1 1 J7A1 2 1 2 1 J9E1 2 1 J1E2 2 1 20. . 23, 27, 36, 42. . 44 +V5 R9G1 0. 01_1% C9G2 22UF +V5_LPCSLOT +V3. 3 R9G5 15, 18. . 20, 23, 27, 30, 32, 35, 38, 39, 43, 44 +V3. 3_LPCSLOT 0. 01_1% C9G4 22UF C8F1 0. 1UF C8F3 0. 1UF C9G3 0. 1UF C9G1 0. 1UF Title Size A LPC Slot & Debug Headers Project: Intel 852GM CRB D Document Number A# 37 of E Rev 59 A B C A B C D E Fan Power Control 8, 15. . 18, 20, 23. . 25, 27, 34, 35, 39, 40, 42, 44, 47 +V5S +V5_FAN Test CAPs 4 6 5 2 1 U1E1 SI3457DV 3 + C1E3 0. 1UF C1E2 22UF J1E1 1 2 CONN2_HDR 1 3 CR1E1 1N4148 4 TP_220pf1 C8J7 220PF TP_330pf1 1 2 C9J3 330PF C8J6 0. 1UF TP_0. 082uf1 C8J4 0. 082uF TP_BS_0. 01uf2 C9Y4 0. 01UF TP_BS_0. 1uf1 TP_BS_0. 1uf2 C9Y5 0. 1UF TP_BS_220pf2 C9Y6 220PF TP_BS_1000pF1 TP_BS_1000pF2 C9Y3 1000PF TP_0. 1uf1 C9J2 TP_0. 01uf1 C9J1 0. 01UF TP_0. 47uf1 1 C8J5 2 0. 47uF TP_220pf2 4 R1E1 1M 3 FAN_ON_Q R1E2 100K C1E4 1000PF FAN_ON_D TP_330pf2 Test CAPs backside TP_BS_100pf1 TP_BS_100pf2 C9Y2 100pF TP_BS_0. 01uf1 TP_0. 1uf1 TP_0. 1uf2 TP_0. 082uf2 32, 37 FAN_ON 1 2 Q1E1 BSS138 TP_0. 47uf2 TP_0. 01uf2 3 TP_BS_220pf1 3 TP_0. 1uf2 0. 1UF System State LEDs 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 39, 40, 42, 44, 48 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 39, 40, 42, 44, 48 +V3. 3S 2 Q1G2 6, 19, 37, 44 PM_SLP_S1# 2 Q2G5 1 S1_LED_C 3 SI2307DS +V3. 3S 15, 18. . 20, 23, 27, 30, 32, 35, 37, 39, 43, 44 5, 15, 19. . 23, 27. . 29, 32, 36, 37, 39, 44, 48 9. . 23, 27. . 29, 32, 36, 37, 39, 44, 48 2 +V3. 3 +V3. 3ALWAYS 19, 25, 32, 37, 43, 44 PM_SLP_S3# 1 R1H1 68 SI2307DS SO_LED_A +V3. 3ALWAYS 2 2 Q2G6 19, 37 PM_SLP_S5# 1 S5_LED_C 3 19, 20, 32, 37, 43, 44 SI2307DS Q2G2 PM_SLP_S4# 1 S4_LED_C 3 SI2307DS PM_SUSLEDPWR 3 2 R1H2 68 2 LED for S0 3 SO_LED_C 1 6, 19, 37, 44 PM_SLP_S1# 1 2 DS1H1 GREEN R2H2 68 2 PM_SUSLED R2H4 68 R2H3 68 2 S4_LED_A 2 S5_LED_A 2 S1_LED_A LED for S1 1 DS1H3 GREEN Q1G1 BSS138 DS2H2 DS2H1 GREEN 13 LED for S5 1 LED for S4 LED for S3 1 DS1H2 GREEN GREEN 1 1 19, 37 PM_SLP_S5# 1 2 Q2G3 BSS138 Title Size A C Fan Circuit, Test Capacitors and System State LEDs Project: Intel 852GM CRB D Document Number A# 38 of E Rev 59 A B A 5, 15, 19. . 23, 27. . 29, 32, 36. . 38, 44, 48 C7A2 0. 1UF U7A3 1 2 +V3. 3ALWAYS B C D E +V3. 3S Step 1 - Power OK C7A4 U7A6 4 74AHC1G08 3 MAIN_PWROK 1 MAIN2_PWROK 74AHC1G08 2 3 5 0. 1UF 5 4 PM_PWROK 19, 21, 25, 32, 37 Step 2 - VR ON 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 38, 40, 42, 44, 48 C4B5 0. 1UF 5 U4B4 32, 37, 42 VR_ON 32 VR_SHUT_DOWN# 1 4 2 74AHC1G08 OFF_BOARD_VR_ON 3 INTERPOSER_PRES# 44 PWR_PWROK 20 V1. 5_PWRGD R4N2 2. 2k U4B5 1 4 2 74AHC1G08 3 5 C4B4 0. 1UF ON_BOARD_VR_ON 40 4 5, 15, 19. . 23, 27. . 29, 32, 36. . 38, 44, 48 C7B2 0. 1UF 43 DDR_VR_PWRGD 21 V5A_PWRGD 1 2 +V3. 3ALWAYS 5 4 U7B1 4 74AHC1G08 3 Step 3 - Power Good 15, 18. . 20, 23, 27, 30, 32, 35, 37, 38, 43, 44 +V3. 3ALWAYS +V3. 3 C7B1 U7A5 4 10K 3 IMVP_PWRGD 7, 40 0. 1UF R2G9 74AHC1G08 IMVP_PWRGD_D 1 +V3. 3S 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 38, 40, 42, 44, 48 R3G10 10K 5, 15, 19. . 23, 27. . 29, 32, 36. . 38, 44, 48 VR PWRGD CIRCUIT 42 GMCH_VCORE_PWRGD C4B2 0. 1UF 40 ON_BOARD_VR_PWRGD INTERPOSER_PRES# 1 74HC00 2 5 7 7 5, 15, 19. . 23, 27. . 29, 32, 36. . 38, 44, 48 14 U4B3C 10 74HC00 9 12 7 OFF_BOARD_VR_PWRGD R4N1 100K 7 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 38, 40, 42, 44, 48 3 H_VID5 +V3. 3S 8 INTERPOSER_PRES 13 74HC00 11 +V3. 3ALWAYS 3 1 2 14 U4B3A PWRGD1 4 74HC00 6 3 Q2G1 2N3904 2 VR_PWRGD_CK408# 6 14 U4B3B 5 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 38, 40, 42, 44, 48 VR_PWRGD 37 4 H_VID[4:0] 8. 2K 7 RP1G1B 2 8. 2K 3 4 6 RP1G1C 8. 2K 5 RP1G1D R1G1 R1H3 8. 2K R1F1 1K 1K BX_PU +V3. 3S 3 Note: J1F1 enables Manual VID strapping 5 4 6 RP1E1D 3 7 RP1E1C 2 8 RP1E1B 1 RP1E1A 8. 2K R1F3 1K U1F1 3 7 11 17 21 4 8 14 18 22 1 13 A0 A1 A2 A3 A4 B0 B1 B2 B3 B4 BE# BX C0 C1 C2 C3 C4 D0 D1 D2 D3 D4 VCC GND 2 6 10 16 20 5 9 15 19 23 24 12 VR_VID0 VR_VID1 VR_VID2 VR_VID3 VR_VID4 34, 40 34, 40 34, 40 34, 40 34, 40 With pin 13 high, B input goes to C output. With pin 13 low, A input goes to C output. 3 14 U4B3D PWRGD2 3 3 J1G2 3 3 1 J1G3 1 1 J1G1 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 38, 40, 42, 44, 48 +V3. 3S CON3_HDR VR_VID5 2 2 4 2 2 J1H7 R1H6 1K 3 2 2 J1H1 3 1 2 J1G4 3 1 1 0 1 CON3_HDR 47 47 47 47 47 STRAP_VID4 STRAP_VID3 STRAP_VID2 STRAP_VID1 STRAP_VID0 STRAP4 STRAP3 STRAP2 STRAP1 STRAP0 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 STRAP_VID0 STRAP_VID1 STRAP_VID2 STRAP_VID3 STRAP_VID4 BE# 2 J1F1 R1F6 8. 2K R1E3 1K 1 BX +V5S 8, 15. . 18, 20, 23. . 25, 27, 3 Bus_Switch_74CBT3383 C1F2 0. 01UF 2 Layout note: Route +VCC_VID to processor with at least a 25 mil trace. R2Y3 330 R2Y2 330 R2Y1 330 R1Y3 330 R1Y2 330 R1Y1 330 VID5_LED VID4_LED VID3_LED DS2J5 DS2J3 DS2J4 GREEN GREEN GREEN 2 2 VID2_LED VID1_LED VID0_LED DS1J1 DS1J2 DS1J3 GREEN GREEN GREEN 2 2 VID5 Setting Processor Control Logic "0" Logic "1" J1H7 1-2 (Default) 2-3 1-X For EVMC use, J1F1 is to be jumpered and J1G1, J1G2, J1G3, J1G4, J1H1 need to be jumpered 1-2 2 2 2 8, 15. . 18, 20, 23. . 25, 27, 34, 35, 38, 40, 42, 44, 47 +V5S 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 38, 40, 42, 44, 48 +V3. 3S J5C2 VR_VID5 VR_VID4 VR_VID3 4, 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VR_VID2 VR_VID1 VR_VID0 1 1 1 1 1 1 3 H_PROCHOT# TP_OFF_BOARD_VCC_VID_PWRGD OFF_BOARD_VR_PWRGD J5C3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 PM_STPCPU# 6, 19, 37, 40 4 PM_DPRSLPVR 19, 37, 40 6 8 SMB_CLK_VR 10 OFF_BOARD_VR_ON 12 14 16 18 R5B4 20 22 NO_STUFF_0 24 26 28 SMB_CLK_S 6, 8, 11, 12, 16, 18 30 32 34 36 38 40 JUMPER SETTINGS DIP Switch Settings 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mobile Northwood VID table DIP Switch Settings +VCC_CORE 1. 750 V 1. 700 V 1. 650 V 1. 600 V 1. 550 V 1. 500 V 1. 450 V 1. 400 V 1. 350 V 1. 300 V 1. 250 V 1. 200 V 1. 150 V 1. 100 V 1. 050 V 1. 000 V 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 +VCC_CORE 0. 975 V 0. 950 V 0. 925 V 0. 900 V 0. 875 V 0. 850 V 0. 825 V 0. 800 V 0. 775 V 0. 750 V 0. 725 V 0. 700 V 0. 675 V 0. 650 V 0. 625 V 0. 600 V +VCC_VID +V3. 3S +V5S +V3. 3S 3 H_VIDPWRGD 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 38, 40, 42, 44, 48 INTERPOSER_PRES# R5B3 6, 8, 11, 12, 16, 18 SMB_DATA_S SMB_DATA_VR 23, 26, 31, 33. . 36, 38, 40, 42, 44, 48 8, 20, 23. . 25, 27, 34, 35, 38, 40, 42, 44, 47 +V5S 8, 15. . 18, 20, 23. . 25, 27, 34, 35, 38, 40, 42, 44, 47 NO_STUFF_0 1 1 16, 21, 40, 44 +VDC 20x2_Header 16, 21, 40, 44 +VDC 20x2_Header Title Size A Processor VR Interposer Support & Power Circuitry Project: Intel 852GM CRB D Connector 2 (rows C, D) A VR Interposer Headers B C Connector 1 (rows A, B) Document Number A# of 39 E Rev 59 A B C D E 4 4 20, 21, 22, 23, 27, 36, 37, 43, 44 +V5 8, 15, 16, 17, 18, 20, 23, 24, 27, 34, 35, 38, 39, 44, 47 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33, 34, 35, 36, 38, 39, 44, 48 +V3. 3S +V5S +VDC 16, 21, 39, 44 +VCC_VID 4, 39 3 34, 39 VR_VID[4:0] 6, 19, 37, 39 PM_STPCPU# , 093 , , , ON_BOARD_VR_PWRGD GMCH_VCORE_PWRGD +VCC_IMVP 3, 4, 5, 9, 10, 18, 20, 47, 48 3 19, 37, 39 PM_DPRSLPVR 39 39 ON_BOARD_VR_ON 9, 10, 47, 48 +V1. 2S_GMCH 32, 37, 39 VR_ON 47 1. 2V_EV 39 2 2 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 38, 39, 42, 44, 48 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 38, 39, 42, 44, 48 +V3. 3S C6C4 0. 1UF R6C13 10K R6C6 1. 58K_1% +V3. 3S VDD+ OPAMP_N 2 10 U6C2A 1 5 OPAMP_EN R6C12 10K TLV2463 DELAYED_VR_PWRGD 19, 37 OPAMP_P 2 7, 39 IMVP_PWRGD 1 Q6C2 BSS84 C6C5 1uF R6C8 2K_1% 3 + GND 4 1 3 1 Title Size A A B C IMVP-III VR Controller Project: Intel 852GM CRB D Document Number A# 40 of E Rev 59 A B C D E Processor Decoupling 3. . 5, 9, 10, 18, 20, 40, 47, 48 4 +VCC_IMVP Bulk decoupling values are tuned to Intel's IMVP III 2 phase VR design. Circuits using other converter topologies may have different requirements. 4 V_CORE Mid and High Frequency Decoupling 3. . 5, 9, 10, 18, 20, 40, 47, 48 C3E2 10UF C2D2 10UF C3T2 10UF C3R9 10UF C3D12 10UF C3R10 10UF C2R5 10UF C3T4 10UF C3T1 10UF C3R6 10UF C3R5 10UF C3D9 10UF C2R1 10UF C3R8 10UF C3R4 10UF C2D3 10UF C3R1 10UF C3R11 10UF C3R3 10UF C3R7 10UF +VCC_IMVP 3. . 5, 9, 10, 18, 20, 40, 47, 48 +VCC_IMVP 3 V_CORE Bulk and Mid Frequency Decoupling C3D10 10UF C3D13 10UF C2T1 10UF C2R4 10UF C3E4 10UF C3D8 10UF V_CORE Mid and High Frequency Decoupling (under CPU) C3T3 10UF C3E1 10UF C2E1 10UF C3E3 10UF C3D5 10UF C3D3 10UF C3D4 10UF C3D2 10UF C2D1 10UF C3R2 10UF C3D11 10UF C3D1 10UF 3 2 2 1 1 Title Size A A B C Processor Decoupling Project: Intel 852GM CRB D Document Number A# 41 of E Rev 59 A B C D E 4 4 3 3 %/$1. 2 2 1 1 Title Size A t A B C Montara-GM VR and VCCP Project: Intel 852GM CRB D Document Number A# of 42 E Rev 59 A B C D E 20. . 23, 27, 36, 37, 42, 44 +V5 BOOT_1 C3G9 C3G7 150uF C3G8 150uF C3G10 0. 1UF 24 23 22 21 20 2 3 4 5 U3G1 VIN0 VIN1 VIN2 VIN3 TPS54610 VIN4 VSENSE NC/Comp PWRGD BOOT RT FSEL PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PwrPad 6 7 8 9 10 11 12 13 14 0. 022uF 9, 11, 12 L4G1 PH_1 1 4. 7uH 2 +V2. 5 Single point sense near load C4F1 0. 1UF 4 C3G5 47pF R3V4 1 25. 5k_1% R3U3 NO_STUFF_10K_1% 2 2 COMP_1_D 1 5600pF RT_1 C3V2 2 VSENSE_1 COMP_1 4 28 27 SS/ENA_1 26 AGND 1 J3G2 R3F22 C3G1 0. 01UF NO_STUFF_10K VBIAS_1 R4G1 5. 49k_1% V2. 5_DDR_D 1 2 CON3_HDR 1 3 19 PGND0 18 PGND1 17 PGND2 16 PGND3 25 15 VBAIS PGND4 Note for layout: This part has special pad on it's underside SS/ENA 20. . 23, 27, 36, 37, 42, 44 11, 12, 47, 48 +V2. 5_DDR 0. 1UF C3F6 +V5 R3V1 10K_1% VSENSE_1_D R3V2 221_1% 1 R3V3 5. 49k_1% 20. . 23, 27, 36, 37, 42, 44 9, 10, 48 +V2. 5_GMCH_SM +V5 1 2 C3V1 8200pF R3F21 43. 2_1% R2G7 VDD+ 10K_1% GND_DDR R3G5 0 2. 5V_DDR_EV 47 Default: J3G1 No Jumper J3G1 1 2 7 SM_VREF_DIMM_EV 47 8 10 U3G2B 9 6 C3G11 0. 1UF R3V8 10K - 3 2 TLV2463 OPAMP1_EN SM_VREF_DIMM 11, 12 3 + GND 4 R3V5 NO_STUFF_10K 9, 10, 48 +V2. 5_GMCH_SM R3G9 0 R3G6 10K_1% 15, 18. . 20, 23, 27, 30, 32, 35, 37. . 39, 44 +V3. 3 R3V11 10K_1% R3G8 10K 20. . 23, 27, 36, 37, 42, 44 DDR_VR_PWRGD 39 +V5 R3W3 10K_1% C3V3 0. 01UF 9, 10, 48 +V2. 5_GMCH_SM SM_VREF_MCH_EV 47 VDD+ 2 10K_1% 3 10 U3G2A TLV2463 1 5 R3V6 NO_STUFF_10K 20. . 23, 27, 36, 37, 42, 44 +V5 REFIN_2 R3G2 - R3G4 OPAMP2_EN 0 + SM_VREF_MCH 7 2 C3H2 150uF C3H3 150uF C3H4 R3W2 0. 1UF NO_STUFF_0 VSENSE_2 C3G13 220PF R3W1 COMP_2_D 4. 99k_1% 0. 082uF FSEL C3V5 BOOT_2 RT_2 5 28 27 26 25 VBIAS_2 R3G12 R3V12 3. 92k_1% R3V9 VSENSE_2_D C3V4 1 2 C3H1 267_1% 8200pF 0. 022uF 19, 20, 32, 37, 38, 44 PM_SLP_S4# R3V10 NO_STUFF_0 100K COMP_2 24 23 22 21 20 2 3 4 U3G3 VIN0 VIN1 VIN2 VIN3 TPS54672 VIN4 VSENSE NC/Comp STATUS BOOT RT ENA PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PwrPad 6 7 8 9 10 11 12 13 14 10K_1% R3G1 GND 4 R3V7 10K 2 Vtt Sense L4H1 PH_2 1 4. 7uH R4H1 2 +VDDR 1. 25V_DDR_EV 47 R4G3 43. 2_1% Single point sense near load 14, 47, 48 +V1. 25S AGND 1 0. 01_1% C6J1 150uF C4J1 150uF C6J2 150uF C4H1 150uF C4H5 0. 1UF 19 PGND0 18 PGND1 17 PGND2 16 PGND3 15 VBAIS PGND4 Note for layout: This part has special pad on it's underside REFIN 19, 25, 32, 37, 38, 44 PM_SLP_S3# R3G11 0 FSEL Non-EV Support EV Support R3G4 R3V7 R3G9 R3V6 R3V6 R3G4 R3V7 R3G9 Stuff C3G12 0. 1UF No Stuff 1 EV Support Resistor Options 1 R3V13 NO_STUFF_4. 99k_1% Vtt Sense Vtt Sense Title Size A DDR VR Project: Intel 852GM CRB D Document Number A# of 43 E Rev 59 A B C A B C D E HDM Connector Assembly (base board) J1B1 A1 A2 A3 A4 D1 D2 D3 D4 F1 F2 F3 F4 3Pin_RECEPTICLE +V1. 8S HDM conn. [. . . ]