User manual INTEL 2ND GENERATION INTEL CORE PROCESSOR FAMILY MOBILE DATASHEET VOLUME 1 01-2011

[. . . ] 2nd Generation Intel® CoreTM Processor Family Mobile Datasheet ­ Volume 1 Supporting Intel® CoreTM i7 Mobile Extreme Edition Processor Series and Intel® CoreTM i5 and i7 Mobile Processor Series This is Volume 1 of 2 January 2011 Document Number: 324692-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Legal Lines and Disclaimers UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. [. . . ] -- And the platform requests a higher power C-state, the memory access or snoop request is serviced and the package remains in the higher power C-state. 52 Datasheet, Volume 1 Power Management Table 4-11 shows package C-state resolution for a dual-core processor. Coordination of Core Power States at the Package Level Core 1 Package C-State C0 C0 C1 Core 0 C3 C6 C7 Note: C0 C0 C0 C0 C0 C1 C0 C11 C11 C11 C11 C3 C0 C11 C3 C3 C3 C6 C0 C11 C3 C6 C6 C7 C0 C11 C3 C6 C7 If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher. Figure 4-3. Package C-State Entry and Exit C0 C 3 C6 C 1 C7 4. 2. 5. 1 Package C0 This is the normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0. Datasheet, Volume 1 53 Power Management 4. 2. 5. 2 Package C1/C1E No additional power reduction actions are taken in the package C1 state. However, if the C1E sub-state is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage. The package enters the C1 low power state when: · At least one core is in the C1 state. The package enters the C1E state when: · All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint. · All cores are in a power state lower that C1/C1E but the package low power state is limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR. · All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is enabled in IA32_MISC_ENABLES. No notification to the system occurs upon entry to C1/C1E. 4. 2. 5. 3 Package C3 State A processor enters the package C3 low power state when: · At least one core is in the C3 state. · The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform. · The platform has not granted a request to a package C6/C7 state but has allowed a package C6 state. In package C3-state, the L3 shared cache is valid. 4. 2. 5. 4 Package C6 State A processor enters the package C6 low power state when: · At least one core is in the C6 state. · The other cores are in a C6 or lower power state, and the processor has been granted permission by the platform. · The platform has not granted a package C7 request but has allowed a C6 package state. In package C6 state, all cores have saved their architectural state and have had their core voltages reduced to zero volts. The processor remains in package C6 state as long as any part of the L3 cache is active. 54 Datasheet, Volume 1 Power Management 4. 2. 5. 5 Package C7 State The processor enters the package C7 low power state when all cores are in the C7 state and the L3 cache is completely flushed. The last core to enter the C7 state begins to shrink the L3 cache by N-ways until the entire L3 cache has been emptied. However, snoops are not sent to the processor in package C7 state because the platform, by granting the package C7 state, has acknowledged that the processor possesses no snoopable information. This allows the processor to remain in this low power state and maximize its power savings. Upon exit of the package C7 state, the L3 cache is not immediately re-enabled. It re-enables once the processor has stayed out of C6 or C7 for an preset amount of time. [. . . ] BGA1224 Processor Ball List by Ball Name Ball Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AF63 AF61 AF11 AF9 AF5 AE57 AD16 AD14 AD7 AD3 AD1 AC64 AC62 AC60 AC57 AB11 AB9 AB5 AA57 AA17 AA15 AA12 Y65 Y63 Y61 Y7 Y3 Y1 W57 V16 V14 V11 V9 V5 U64 U62 U60 U57 T7 T3 T1 R57 R50 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Dir Table 8-2. BGA1224 Processor Ball List by Ball Name Ball Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # R44 R38 R31 R25 R19 R17 R15 R12 P65 P63 P61 P11 P9 P5 N54 N47 N41 N35 N28 N22 M57 M50 M44 M38 M31 M25 M19 M7 M3 M1 L64 L62 L60 L58 L54 L50 L46 L42 L36 L30 L24 L20 L16 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Dir Datasheet, Volume 1 139 Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name Ball Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # L12 L8 K39 K33 K27 K1 J64 J60 J56 J52 J48 J46 J42 J36 J30 J24 J22 J18 J14 J10 J6 H39 H33 H27 H3 G62 G58 G54 G50 G46 G42 G36 G30 G24 G20 G16 G12 G8 F39 F33 F27 E60 E56 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Dir Table 8-2. BGA1224 Processor Ball List by Ball Name Ball Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_NCTF VSS_NCTF Ball # E52 E48 E46 E42 E36 E30 E24 E22 E18 E14 E10 E6 E4 D63 D39 D33 D27 C58 C54 C50 C46 C42 C36 C30 C20 C16 C12 C8 B39 B33 B27 A56 A52 A42 A36 A30 A24 A20 A16 A12 A8 BJ60 BJ6 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Dir 140 Datasheet, Volume 1 Processor Pin and Signal Information Table 8-2. [. . . ]